Bidirectional shift registers capable of producing bidirectional shift pulse outputs are conventionally known. Also known are those which are arranged to produce inspection signal outputs to inspect the operation of a bidirectional shift register.
FIG. 16 is a block diagram showing a display device incorporating a bidirectional shift register arranged to produce inspection signal outputs. A display device 51, as shown in FIG. 16, includes a data signal line drive circuit 52, a scan signal line drive circuit 53, and a display device section 54.
The data signal line drive circuit 52 includes a bidirectional shift register 61, a buffer section 62, and a sampling section 63. The bidirectional shift register 61 includes a shift register section 64 and an inspection signal switching section 65.
The shift register section 64 is a shift register capable of switching its shift direction in accordance with a horizontal instruction signal LR. The shift register section 64 outputs pulse signals SR1, SR2, . . . SRn to the buffer section 62 on the basis of a horizontal shift start signal SSP and a timing-providing horizontal clock signal SCK which has a predetermined cycle.
The horizontal clock signal SCK and the horizontal shift start signal SSP are both rectangular. The pulse signals SR1, SR2, . . . SRn are therefore also rectangular.
The buffer section 62 amplifies the current levels of the pulse signals SR1, SR2, . . . SRn. The amplified outputs of the buffer section 62 are fed to the sampling section 63 where video signals VIDEO_R, VIDEO_G, and VIDEO_B separately fed to the sampling section 63 are sampled in accordance with the outputs of the buffer section 62 and supplied to data signal lines in the display device section 54.
The inspection signal switching section 65 switches a shift end signal ADOUT between the last stage outputs (SR1, SRn) of the shift register section 64 in accordance with the horizontal instruction signal LR for output to external circuitry. The inspection signal switching section 65 will be detailed later.
The scan signal line drive circuit 53 includes a bidirectional shift register 71 and a buffer section 72. The bidirectional shift register 71 includes a shift register section 74 and an inspection signal switching section 75.
The shift register section 74 is a shift register capable of switching its shift direction in accordance with a vertical instruction signal UD. The shift register section 74 outputs pulse signals GL1, GL2, . . . GLm to the buffer section 72 on the basis of a vertical direction shift start signal GSP and a timing-providing vertical direction clock signal GCK which has a predetermined cycle.
The vertical direction clock signal GCK and the vertical direction shift start signal GSP are both rectangular. The pulse signals SR1, SR2, . . . SRn are therefore also rectangular.
The buffer section 72 amplifies the current levels of the pulse signals GL1, GL2, . . . GLm. The amplified outputs of the buffer section 72 are fed to scan signal lines in the display device section 54.
The inspection signal switching section 75 switches a shift end signal GDOUT between the last stage outputs (GL1, GLm) of the shift register section 74 in accordance with the horizontal instruction signal LR for output to external circuitry.
As in the foregoing, the bidirectional shift register 61 has the same arrangement as the bidirectional shift register 71, except for the number of output signals. The following description will therefore focus on the data signal line drive circuit 52 including the bidirectional shift register 61.
FIG. 17 is a circuit diagram showing an arrangement of the shift register section 64 in the bidirectional shift register 61. As illustrated in the figure, the shift register section 64 includes a set of flip-flops FF1, FF2, . . . FFn, a group, AS1, of n analog switches 81, and another group, AS2, of n analog switches 82.
The analog switches 81, 82 change the destinations for the signal outputs of the flip-flop FF1, FF2, . . . FFn in accordance with the horizontal instruction signal LR.
FIG. 18 is a circuit diagram showing an arrangement of the analog switch 81.
As shown in the figure, each analog switch 81 is composed of a CMOS analog switch 81a and an inverter 81b. In the analog switch 81, when the incoming horizontal instruction signal LR is HIGH on the control line CTL, the signal applied to the IN appears unchanged at the OUT. In contrast, when the horizontal instruction signal LR is LOW on the control line CTL, the impedance so increases (Hi-Z state) that whatever signal is applied to the IN, no output appears at the OUT, i.e., the OUT floats.
FIG. 19 is a circuit diagram showing an arrangement of the analog switch 82.
As shown in the figure, each analog switch 82 is also composed of a CMOS analog switch 81a and an inverter 81b. The analog switch 82 however differs from the analog switch 81 in the layout of the inverter 81b. 
In the analog switch 82, when the incoming horizontal instruction signal LR is LOW on the control line CTL, the signal applied to the IN appears unchanged at the OUT as an output. In contrast, when the horizontal instruction signal LR is HIGH on the control line CTL, the impedance so increases (Hi-Z state) that whatever signal is applied to the IN, no output appears at the OUT, i.e., the OUT floats.
FIG. 20 is a diagram showing signal flows in the shift register section 64 when the horizontal instruction signal LR is HIGH.
Since the horizontal instruction signal LR is HIGH, as mentioned earlier, only the analog switches 81 constituting the group AS1 allow the input signal at the IN to appear at the OUT as an output. A pulse signal therefore flows as indicated by thick lines in the figure. In other words, the horizontal shift start signal SSP travels from the flip-flop FF1 to the flip-flop FFn in this order.
FIG. 21 is a diagram showing signal flows in the shift register section 64 when the horizontal instruction signal LR is LOW.
Since the horizontal instruction signal LR is LOW, as mentioned earlier, only the analog switches 82 constituting the group AS2 allow the input signal at the IN to appear at the OUT as an output. A pulse signal therefore flows as indicated by thick lines in the figure. In other words, the horizontal shift start signal SSP travels from the flip-flop FFn to the flip-flop FF1 in this order.
As in the foregoing, in the bidirectional shift register 61, the last output stage of the shift register section 64 is the one which outputs the pulse signal SRn when the horizontal instruction signal LR is HIGH and the one which outputs the pulse signal SR1 when the horizontal instruction signal LR is LOW.
FIG. 22 is a circuit diagram showing an arrangement of the buffer section 62 and the sampling section 63 in the data signal line drive circuit 52. As shown in the figure, the buffer section 62 is composed of a set of inverters. The sampling section 63 is composed of CMOS analog switches. Further detailed description of the buffer section 62 and the sampling section 63 is omitted here.
FIG. 23 is a circuit diagram showing an arrangement of the inspection signal switching section 65.
The inspection signal switching section 65 is composed of two CMOS analog switches 81a and an inverter 81b. In the analog switch 81, when the incoming horizontal instruction signal LR is HIGH on the control line CTL, the signal applied to the IN1 appears unchanged at the OUT. In contrast, when the horizontal instruction signal LR is LOW on the control line CTL, the signal applied to the IN2 appears unchanged at the OUT.
Incidentally, the operation of a bidirectional shift register which predates the bidirectional shift register 61 is verified by means of signal outputs at inspection terminals provided to the first and last output stages for signal inspection purposes. The first and last output stages in the shift register act similarly to the stage outputting the pulse signal SR1 and the stage outputting the pulse signal SRn in the bidirectional shift register 61.
If a bidirectional shift register with inspection terminals on the first and last output stages is used in a display device, in view of display device protection, the inspection terminals on the first and last output stages need to be, for example, treated so as to float with respect to the flexible wiring board, i.e., the terminals do not connect to anything, as shown in FIG. 24(a).
This arrangement requires more inspection terminals than the arrangement in FIG. 24(b) where only one inspection terminal is needed to verify the operation of a bidirectional shift register. Thus, the flexible wiring board needs to accommodate more terminals. These factors can amount to an increase, albeit small, in the price of the flexible wiring board.
In FIGS. 24(a), 24(b), black portions correspond to the wiring on the flexible wiring board or the inspection terminal(s) for the display device.
In addition, in in-line verification of the operation of a bidirectional shift register, signal detection probes need to be used to test inspection terminals as shown in FIG. 25. The inspection terminals, including those on the first and last output stages, need to be located, for example, at 500 μm intervals.
If the inspection terminals are reduced in size, it takes a significantly long time to position the signal detection probes, which makes the approach less competitive in terms of cost.
For these reasons, in the bidirectional shift register 61, the inspection signal switching section 65 having the aforementioned arrangement is provided, the output of the stage outputting the pulse signal SRn is coupled to the IN1 as an input, and the output of the stage outputting the pulse signal SR1 is coupled to the IN2 as an input.
Thus, when the horizontal instruction signal LR is HIGH, the output of the stage outputting the pulse signal SRn can be fed as a shift end signal ADOUT to external circuitry; when the horizontal instruction signal LR is LOW, the output of the stage outputting the pulse signal SR1 can be fed as a shift end signal ADOUT to external circuitry.
In this manner, no matter whether the horizontal instruction signal LR is High or Low, the bidirectional shift register 61 outputs a shift end signal ADOUT which is the output of the last stage. Hence, in verifying that the pulse signal reaches the last output stage, the bidirectional shift register 61 only requires the inspection terminals where the shift end signal ADOUT is inspected.
FIG. 26 is a timing chart showing an operation of the bidirectional shift register 61, particularly when the horizontal instruction signal LR changes from HIGH to LOW during an operation.
As shown in the figure as well as FIG. 16, when the horizontal instruction signal LR is HIGH, the pulse signal SRn is simultaneously fed to both the buffer section 62 and external circuitry as a shift end signal ADOUT via the inspection signal switching section 65.
When the horizontal instruction signal LR is LOW, the pulse signal SR1 is simultaneously fed to both the buffer section 62 and external circuitry as a shift end signal ADOUT via the inspection signal switching section 65.
No matter which state the horizontal instruction signal LR is representing, the bidirectional shift register 61 causes an invariant time delay between the input of the horizontal shift start signal SSP and the output of the shift end signal ADOUT.
U.S. Pat. No. 6,724,363 dated Apr. 20, 2004, an equivalent to Japanese unexamined patent application 2000-322020 (Tokukai 2000-322020; published on Nov. 24, 2000), discloses a power-saving bidirectional shift register which operates normally with input signals of small amplitudes.
Japanese unexamined patent application 8-62580 (Tokukaihei 8-62580/1996; published on Mar. 8, 1996) discloses a display device element with such internal circuitry that the number of inspection terminals can be reduced.
However, although the bidirectional shift register 61 has received an instruction to change the state of the horizontal instruction signal LR, if the horizontal instruction signal LR is fixed in LOW state due to, for example, a defect of internal circuitry of the bidirectional shift register 61, following problems result among others.
Under these conditions, the shift end signal ADOUT output of the bidirectional shift register 61 has the same waveform as the shift end signal ADOUT output of a normal bidirectional shift register 61 (compare FIG. 27 with FIG. 26).
If the horizontal instruction signal LR is fixed in HIGH state due to for example, a defect of internal circuitry of the bidirectional shift register 61, the shift end signal ADOUT output of the bidirectional shift register 61 again has the same waveform as the shift end signal ADOUT output of a normal bidirectional shift register 61 (compare FIG. 28 with FIG. 26).
As in the foregoing, in the bidirectional shift register 61, the pulse signal can be determined to have reached the last stage in both directions in a normal manner even if the bidirectional shift register 61 is not normally responding to the horizontal instruction signal LR.
To manufacture a liquid crystal display device incorporating the bidirectional shift register 61, for example, the bidirectional shift register 61 is fabricated on a board, which is followed by a “liquid crystal step” where the display device element is fabricated on the same board. Thereafter, the display device 51 is turned on for an inspect in which produced displays are checked.
Therefore, when the bidirectional shift register 61 is not normally operating as in the above example, the defect of the bidirectional shift register 61 cannot be found until the register 61 is turned on for inspection.
The liquid crystal step is wasted, making it difficult to lower the manufacturing cost of the display device 51.
Neither Tokukai 2000-322020 nor Tokukaihei 8-62580/1996 disclose technology addressing these problems.